[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.
authorAmara Emerson <amara@apple.com>
Wed, 18 Aug 2021 07:19:58 +0000 (00:19 -0700)
committerAmara Emerson <amara@apple.com>
Thu, 19 Aug 2021 23:38:52 +0000 (16:38 -0700)
commit95ac3d15e9fe86d9b51b51d02cb3c1640bf30dee
treeeb928600c2d369838959eb0ada71055ff07e0dcb
parentfbb8e772ec501a1b71643db90e9c6445e17d7cac
[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.

For some reductions like G_VECREDUCE_OR on AArch64, we need to scalarize
completely if the source is <= 64b. This change adds support for that in
the legalizer. If the source has a pow-2 num elements, then we can do
a tree reduction using the scalar operation in the individual elements.
Otherwise, we just create a sequential chain of operations.

For AArch64, we only need to scalarize if the input is <64b. If it's great than
64b then we can first do a fewElements step to 64b, taking advantage of vector
instructions until we reach the point of scalarization.

I also had to relax the verifier checks for reductions because the intrinsics
support <1 x EltTy> types, which we lower to scalars for GlobalISel.

Differential Revision: https://reviews.llvm.org/D108276
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/reduce-or.ll
llvm/test/MachineVerifier/test_vector_reductions.mir