drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
authorKuogee Hsieh <khsieh@codeaurora.org>
Tue, 18 Jan 2022 18:47:27 +0000 (10:47 -0800)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fri, 18 Feb 2022 15:32:58 +0000 (18:32 +0300)
commit956653250b21ccd6dfbeba7fd6d5422de743a5b5
tree733f35c2fdb358afd0d32048c20b4eec4b482f51
parent5e602f5156910c7b19661699896cb6e3fb94fab9
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3

Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.

Changes in V2:
-- replace  dp_catalog_ctrl_set_pattern() with  dp_catalog_ctrl_set_pattern_state_bit()

Changes in V3:
-- change state_ctrl_bits type to u32 and pattern type to u8

Changes in V4:
-- align } else if { and } else {

Changes in v10:
--  group into one series

Changes in v11:
-- drop drm/msm/dp: dp_link_parse_sink_count() return immediately if aux read

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1642531648-8448-4-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/dp/dp_catalog.c
drivers/gpu/drm/msm/dp/dp_catalog.h
drivers/gpu/drm/msm/dp/dp_ctrl.c