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(parent: 8e17c96) | patch
[RISCV] Fix incorrect MemOperand copy converting splat+load to vlse.
authorCraig Topper <craig.topper@sifive.com>
Thu, 17 Feb 2022 16:10:20 +0000 (08:10 -0800)
committerCraig Topper <craig.topper@sifive.com>
Thu, 17 Feb 2022 16:15:50 +0000 (08:15 -0800)
commit954fe404ab7f5dab917fe7987f68a3095ba10413
tree043f2029f87cb715c190f6aaa16c2098dcb0a72ctree | snapshot
parent8e17c9613f36f23b5a9d2720f330a37e54c6924fcommit | diff
[RISCV] Fix incorrect MemOperand copy converting splat+load to vlse.

Due to an incorrect copy/paste from load intrinsic handling we
checked if the splat node was a MemSDNode which of course it isn't.

Instead get the MemOperand from the LoadSDNode for the source of
the splat.

This enables LICM to see the load is loop invariant and hoist it
out of the loop.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D120014
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll diff | blob | history
Domain: System / Toolchain;