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(parent: 8a4e24e) | patch
ARM: relax the atomic release barrier to "dmb ishst"
authorTim Northover <tnorthover@apple.com>
Mon, 1 Jul 2013 14:48:48 +0000 (14:48 +0000)
committerTim Northover <tnorthover@apple.com>
Mon, 1 Jul 2013 14:48:48 +0000 (14:48 +0000)
commit953abab40ae89d546a379fa97afe6dea483e851a
tree5db8f9756cabd9087db5f0a5ed8455bab444769btree | snapshot
parent8a4e24ea8b9d7059fa0a8b0a3ce3b838115dcc4acommit | diff
ARM: relax the atomic release barrier to "dmb ishst"

I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.

A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.

llvm-svn: 185339
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/test/CodeGen/ARM/atomic-64bit.ll diff | blob | history
llvm/test/CodeGen/ARM/atomic-load-store.ll diff | blob | history
Domain: System / Toolchain;