MachineVerifier: Verify REG_SEQUENCE
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 21 Sep 2022 14:42:03 +0000 (10:42 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 22 Sep 2022 13:51:15 +0000 (09:51 -0400)
commit94ebd7d9ff1776bbc94ca6ac82a783fa9d4eaa72
tree8ec4d1605b39e27926c3b7b15bedf148dc63b343
parentc2e76f914c9ac0dd15e4a8040a5e277333f91f97
MachineVerifier: Verify REG_SEQUENCE

Somehow there was no verification of this, other than an ad-hoc
assertion in TwoAddressInstructions.
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/test/CodeGen/AMDGPU/load-store-opt-dlc.mir
llvm/test/CodeGen/AMDGPU/load-store-opt-scc.mir
llvm/test/CodeGen/MIR/X86/subregister-index-operands.mir
llvm/test/MachineVerifier/verify-reg-sequence.mir [new file with mode: 0644]