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arm64: tegra: Add MISC registers on Tegra186
authorThierry Reding <treding@nvidia.com>
Mon, 26 Jun 2017 15:37:09 +0000 (17:37 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 13 Dec 2017 12:15:42 +0000 (13:15 +0100)
commit94e25dc3a2b55eb9732f6da41bd25b9dccd60b5a
tree4555b6e7dfff6afacc25d3ddbc53c2c3f5d3ac44tree | snapshot
parent029ab5eaf091ce5eaa1f3017f66fd1d10f431d61commit | diff
arm64: tegra: Add MISC registers on Tegra186

The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.

Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra186.dtsi diff | blob | history
Domain: System / Kernel;