powerpc/t4qds: Add alternate serdes protocols to align with A-007186
authorShaohui Xie <Shaohui.Xie@freescale.com>
Fri, 16 May 2014 02:52:33 +0000 (10:52 +0800)
committerYork Sun <yorksun@freescale.com>
Thu, 5 Jun 2014 19:55:59 +0000 (12:55 -0700)
commit94752f60eb0d17d30dd1dbc81dac42d9119f5b36
tree242bcdeb0dfa9ca33baa4eeb7fbe85ec6934ff11
parent9752eb64260cb51b8c87dcddc73e6270a494e073
powerpc/t4qds: Add alternate serdes protocols to align with A-007186

A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V
(or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC
VCO. Only the protocols using Ring VCOs are impacted.

Workaround:
For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need
to use alternate serdes protocols. The alternate option has the same
functionality as the original option; the only difference being LC VCO
rather than Ring VCO.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
board/freescale/t4qds/eth.c
board/freescale/t4qds/t4240qds.c
board/freescale/t4qds/t4_rcw.cfg