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(parent: c9d2b6b) | patch
[mlir][sparse] Avoid generating DimOp in conversion passes.
authorPeiming Liu <peiming@google.com>
Fri, 9 Sep 2022 17:29:16 +0000 (17:29 +0000)
committerPeiming Liu <peiming@google.com>
Fri, 9 Sep 2022 18:08:05 +0000 (18:08 +0000)
commit938f419cf1910b79388896c9694e58efc5325cba
tree2bb957c5e53baa9c3052ae966ea913303c35e877tree | snapshot
parentc9d2b6b92d6c29d00f6adc0527cf2331dbaae31acommit | diff
[mlir][sparse] Avoid generating DimOp in conversion passes.

Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D133592
mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp diff | blob | history
mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp diff | blob | history
Domain: System / Toolchain;