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(parent: 89cd7ae) | patch
clk: mediatek: update missing clock data for MT7622 audsys
authorRyder Lee <ryder.lee@mediatek.com>
Tue, 6 Mar 2018 09:09:26 +0000 (17:09 +0800)
committerStephen Boyd <sboyd@kernel.org>
Mon, 19 Mar 2018 20:40:57 +0000 (13:40 -0700)
commit936ceb12c5f72cd087149e3cf01347969a472801
tree25255cf397c5ceef3f7ad9765e7d73efd263d61dtree | snapshot
parent89cd7aec21af26fd0c117bfc4bfc781724f201decommit | diff
clk: mediatek: update missing clock data for MT7622 audsys

Add missing clock data 'CLK_AUDIO_AFE_CONN' for MT7622 audsys.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/clk-mt7622-aud.c diff | blob | history
include/dt-bindings/clock/mt7622-clk.h diff | blob | history
Domain: System / Kernel;