[PowerPC] Exploit xxperm, check for dead vectors and substitute vperm with xxperm
authorMaryam Moghadas <maryammo@ca.ibm.com>
Mon, 12 Sep 2022 14:27:57 +0000 (09:27 -0500)
committerMaryam Moghadas <maryammo@ca.ibm.com>
Wed, 23 Nov 2022 19:28:12 +0000 (13:28 -0600)
commit934d5fa2b8672695c335deed0e19d0e777c98403
tree182b3055840f212c984a8759eb5603e25939488b
parentfa7bc386ec7565ccfdfa75b272079ee03604e3ba
[PowerPC] Exploit xxperm, check for dead vectors and substitute vperm with xxperm

vperm instruction requires the data to be in the Altivec registers, if one of
the vector operands is not used after this vperm instruction then it can be
substituted by xxperm which doubles the number of available registers.

Reviewed By: stefanp

Differential Revision: https://reviews.llvm.org/D133700
34 files changed:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
llvm/test/CodeGen/PowerPC/build-vector-tests.ll
llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
llvm/test/CodeGen/PowerPC/extract-and-store.ll
llvm/test/CodeGen/PowerPC/load-and-splat.ll
llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll
llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll
llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll
llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll
llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
llvm/test/CodeGen/PowerPC/vec-itofp.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
llvm/test/CodeGen/PowerPC/vec_extract_p9.ll
llvm/test/CodeGen/PowerPC/vec_int_ext.ll
llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll