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(parent: c1ae3cf) | patch
clk: tegra: Fix pll_a1 iddq register, add pll_a1
authorPeter De Schrijver <pdeschrijver@nvidia.com>
Thu, 23 Feb 2017 10:44:38 +0000 (12:44 +0200)
committerThierry Reding <treding@nvidia.com>
Mon, 20 Mar 2017 13:04:27 +0000 (14:04 +0100)
commit9326947f2215e1816a9133b0b47e4c9200552777
treee2aebbe96a3976767a69c22346b0a6315cf3a58atree | snapshot
parentc1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201commit | diff
clk: tegra: Fix pll_a1 iddq register, add pll_a1

pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add
pll_a1 to the set of clocks defined for Tegra210.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c diff | blob | history
Domain: System / Kernel;