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(parent: 0d67871) | patch
phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY
authorRohit Agarwal <quic_rohiagar@quicinc.com>
Fri, 17 Mar 2023 06:38:34 +0000 (12:08 +0530)
committerVinod Koul <vkoul@kernel.org>
Fri, 31 Mar 2023 13:54:24 +0000 (19:24 +0530)
commit92bd868f529a7771f15a141e8db6b6b62b32310a
tree950f93ed4adf4539fbc135b39705b0645feb146btree | snapshot
parent0d678713118352614b14aba0c1fb066b1ba39f53commit | diff
phy: qcom-qmp: Add support for SDX65 QMP PCIe PHY

The PCIe PHY version used in SDX65 is v5.20 which has different register
offsets compared to the v5.0x and v4.0x PHYs. So separate register defines are
used for init sequence and PHY status.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1679035114-19879-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c diff | blob | history
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h diff | blob | history
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h diff | blob | history
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_20.h diff | blob | history
Domain: System / Kernel;