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[clang-format] Handle enum in Verilog
authorsstwcw <f0gukp2nk@protonmail.com>
Sat, 1 Apr 2023 17:08:31 +0000 (17:08 +0000)
committersstwcw <f0gukp2nk@protonmail.com>
Sat, 1 Apr 2023 17:09:44 +0000 (17:09 +0000)
commit92b2be39656b9d5c6b57b844884f3bcf3e44f6cd
tree61dd0d06cd2f50a39f5fc845cc1e4bc2b5545cfdtree | snapshot
parent5888a47914f44ffaf102fcb7afd3500706fe753fcommit | diff
[clang-format] Handle enum in Verilog

Verilog has enum just like C.

Reviewed By: HazardyKnusperkeks, owenpan, MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D147328
clang/lib/Format/UnwrappedLineParser.cpp diff | blob | history
clang/unittests/Format/FormatTestVerilog.cpp diff | blob | history
Domain: System / Toolchain;