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dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
authorXingyu Wu <xingyu.wu@starfivetech.com>
Tue, 14 Mar 2023 12:43:57 +0000 (20:43 +0800)
committerJaehoon Chung <jh80.chung@samsung.com>
Mon, 24 Jul 2023 23:24:34 +0000 (08:24 +0900)
commit9260c598b346998f819e0e9dce07cb4d9e3b93fa
tree524b3f6d5e76b9c5cdf24c0ad3665993350c534ctree | snapshot
parent468ce97b7c8f0a3f1a176f7a72571ec39e2b4cd6commit | diff
dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml [new file with mode: 0644] blob
include/dt-bindings/clock/starfive,jh7110-crg.h diff | blob | history
include/dt-bindings/reset/starfive,jh7110-crg.h diff | blob | history
Domain: System / Kernel;