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clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte src
authorKonrad Dybcio <konrad.dybcio@somainline.org>
Mon, 10 Oct 2022 15:55:46 +0000 (17:55 +0200)
committerBjorn Andersson <andersson@kernel.org>
Sun, 6 Nov 2022 03:21:59 +0000 (22:21 -0500)
commit92039e8c080c63748f8e133e7cfad33a75daefb6
tree0676bf1a1e5cda0c741539981705d4d608d86a46tree | snapshot
parent6db4d77f5701699aa6eb4e9718d69a7a55f0aa65commit | diff
clk: qcom: dispcc-sm6350: Add CLK_OPS_PARENT_ENABLE to pixel&byte src

Add the CLK_OPS_PARENT_ENABLE flag to pixel and byte clk srcs to
ensure set_rate can succeed.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for  SM6350")
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221010155546.73884-1-konrad.dybcio@somainline.org
drivers/clk/qcom/dispcc-sm6350.c diff | blob | history
Domain: System / Kernel;