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RISC-V: Fix vsetivli instruction asm for IMM AVL
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Tue, 3 Jan 2023 01:39:57 +0000 (09:39 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Thu, 26 Jan 2023 18:53:00 +0000 (02:53 +0800)
commit91a41201b5cea1d72cd84e0e8751289774fcba42
tree649e328840235e23bfcd3a3cc45d2d53b33f51d8tree | snapshot
parent856eec0d6b65c7b28b4b6c4fd6ccc10f2f6a22b1commit | diff
RISC-V: Fix vsetivli instruction asm for IMM AVL

Notice that we should used vsetivli zero,4 instead of vsetvli zero,4
for IMM AVL (0 ~ 31) according to RVV ISA.

This patch fix vsetivli instruction asm bug.

gcc/ChangeLog:

* config/riscv/vector.md:

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vle-constraint-1.c:
gcc/config/riscv/vector.md diff | blob | history
gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c diff | blob | history
Domain: System / Toolchain;