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(parent: 7b3b178) | patch
[RISCV] Add X1 as implicit def of cm.jalt.
authorCraig Topper <craig.topper@sifive.com>
Fri, 5 May 2023 17:08:47 +0000 (10:08 -0700)
committerCraig Topper <craig.topper@sifive.com>
Fri, 5 May 2023 17:08:47 +0000 (10:08 -0700)
commit913b95fb80853894c479753f4f03a5efd3b0a5c8
tree393d1d67e97d3e4b7dfa90c4a0d2a63e1eb06c39tree | snapshot
parent7b3b178c825bfcf196685311bf33e4a5fa8ca8aacommit | diff
[RISCV] Add X1 as implicit def of cm.jalt.

This instruction updates the RA register.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149933
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td diff | blob | history
Domain: System / Toolchain;