[AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...
authorVladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com>
Tue, 7 Feb 2023 16:48:58 +0000 (17:48 +0100)
committerVladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com>
Tue, 7 Feb 2023 20:33:44 +0000 (21:33 +0100)
commit90c98f8e5516901cd5dbd677e65fb8d7dd483cba
tree0864151d57db524b6a5f3b47d5c6cc4c966366e1
parent836249b1c2f0540ed0c886d6c3558b2f4f179249
[AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...

Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD,
G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors.

Fixes https://github.com/llvm/llvm-project/issues/58156.

Differential Revision: https://reviews.llvm.org/D143517
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir