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(parent: ced7af9) | patch
clk: samsung: exynos4: Add support for PLL46xx rate configuration
authorTomasz Figa <t.figa@samsung.com>
Tue, 14 May 2013 17:20:03 +0000 (19:20 +0200)
committerChanho Park <chanho61.park@samsung.com>
Tue, 18 Nov 2014 02:42:39 +0000 (11:42 +0900)
commit9007b2a25ae785423fc06e1d1395886a31a15d13
treeb0075764389928a232b258d48e8c2c9fb47d0555tree | snapshot
parentced7af9360beb49d2309df130f0713ec53c26888commit | diff
clk: samsung: exynos4: Add support for PLL46xx rate configuration

This patch adds support for rate configuration of PLL46xx, which is used
for EPLL and VPLL on Exynos4210.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
drivers/clk/samsung/clk-exynos4.c diff | blob | history
drivers/clk/samsung/clk-pll.c diff | blob | history
drivers/clk/samsung/clk-pll.h diff | blob | history
Domain: System / Kernel;