projects / platform / kernel / linux-exynos.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: fb1cecd) | patch
ARM: dts: r8a7791: Add L2 cache-controller node
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 2 Jun 2015 12:33:46 +0000 (14:33 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Fri, 19 Feb 2016 05:52:22 +0000 (14:52 +0900)
commit8ffe93a5b2cb55d4da9c285d9277699bdb828b47
tree873ad3e0e94e30f402c550fe694fa41b6f22e407tree | snapshot
parentfb1cecd40690e61e122d7249e7499c8d799feffbcommit | diff
ARM: dts: r8a7791: Add L2 cache-controller node

Add a device node for the L2 cache, and link the CPU nodes to it.

The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7791.dtsi diff | blob | history
Domain: System / Kernel;