RISC-V: Detect AIA CSRs from ISA string
authorAnup Patel <apatel@ventanamicro.com>
Mon, 6 Mar 2023 06:40:15 +0000 (12:10 +0530)
committerAnup Patel <anup@brainfault.org>
Fri, 21 Apr 2023 12:15:42 +0000 (17:45 +0530)
commit8fe6f7e14c7eeb01c3a1994eba2356400981cb1e
tree574862e1bc8bea264ecc2715322ad501d1c0b852
parentd6f5f6e904be628941eeab7d6ae7d1fb9190c486
RISC-V: Detect AIA CSRs from ISA string

We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs)
and Ssaia (S-mode AIA CSRs).

We extend the ISA string parsing to detect Smaia and Ssaia extensions.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpu.c
arch/riscv/kernel/cpufeature.c