drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang
authorColin Xu <colin.xu@intel.com>
Mon, 12 Oct 2020 04:52:31 +0000 (12:52 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Mon, 19 Oct 2020 08:54:11 +0000 (16:54 +0800)
commit8fe105679765700378eb328495fcfe1566cdbbd0
tree986b55bc0f17d2903533f1dfdf0dea6830759a66
parent97f9ca383dca6f4b425fb3c4709405fb8272a15f
drm/i915/gvt: Set SNOOP for PAT3 on BXT/APL to workaround GPU BB hang

If guest fills non-priv bb on ApolloLake/Broxton as Mesa i965 does in:
717e7539124d (i965: Use a WC map and memcpy for the batch instead of pw-)
Due to the missing flush of bb filled by VM vCPU, host GPU hangs on
executing these MI_BATCH_BUFFER.

Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
PML4 PTE: PAT(0) PCD(1) PWT(1).

The performance is still expected to be low, will need further improvement.

Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20201012045231.226748-1-colin.xu@intel.com
drivers/gpu/drm/i915/gvt/handlers.c