Add OffsetIsScalable to getMemOperandWithOffset
authorSander de Smalen <sander.desmalen@arm.com>
Tue, 18 Feb 2020 14:32:26 +0000 (14:32 +0000)
committerSander de Smalen <sander.desmalen@arm.com>
Tue, 18 Feb 2020 15:53:29 +0000 (15:53 +0000)
commit8fbc92580769dd42b4f00fd41200e0fa9de98405
tree6c72cdeff2e0b517e8508106636f4a19df15b0e6
parent5e52effca6289a438a2751db532d625097cc6af7
Add OffsetIsScalable to getMemOperandWithOffset

Summary:
Making `Scale` a `TypeSize` in AArch64InstrInfo::getMemOpInfo,
has the effect that all places where this information is used
(notably, TargetInstrInfo::getMemOperandWithOffset) will need
to consider Scale - and derived, Offset - possibly being scalable.

This patch adds a new operand `bool &OffsetIsScalable` to
TargetInstrInfo::getMemOperandWithOffset and fixes up all
the places where this function is used, to consider the
offset possibly being scalable.

In most cases, this means bailing out because the algorithm does not
(or cannot) support scalable offsets in places where it does some
form of alias checking for example.

Reviewers: rovka, efriedma, kristof.beyls

Reviewed By: efriedma

Subscribers: wuzish, kerbowa, MatzeB, arsenm, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, javed.absar, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72758
19 files changed:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/lib/CodeGen/ImplicitNullChecks.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/ModuloSchedule.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.h
llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
llvm/lib/Target/Lanai/LanaiInstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h