projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d8ffb1f) | patch
[RISCV] Add test cases for missed opportunities to use sbsetw/sbclrw/sbinvw when...
authorCraig Topper <craig.topper@sifive.com>
Thu, 26 Nov 2020 09:54:07 +0000 (01:54 -0800)
committerCraig Topper <craig.topper@sifive.com>
Thu, 26 Nov 2020 10:03:06 +0000 (02:03 -0800)
commit8fb8fb2c607794fe4cde69713f2fa556f613dab1
treefa3f31086ae36d8647e8c7bb48994e79e55e0ec6tree | snapshot
parentd8ffb1f6a7572b64d5fa6b821c5c143e0e90bb6dcommit | diff
[RISCV] Add test cases for missed opportunities to use sbsetw/sbclrw/sbinvw when the result isn't known to be sign extended.

If the input isn't sign extended, but the output of the or/xor/and
is used by a sign_inreg we can still use sbsetw/sbclrw/sbinvw.
llvm/test/CodeGen/RISCV/rv64Zbs.ll diff | blob | history
Domain: System / Toolchain;