[AArch64][GlobalISel] Add support for some across-vector NEON intrinsics
authorVladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com>
Tue, 28 Mar 2023 13:57:35 +0000 (15:57 +0200)
committerVladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com>
Wed, 5 Apr 2023 10:59:55 +0000 (12:59 +0200)
commit8f5db5332b2a4e9465f12e3192120eb28935e1a0
tree6961c83e63a16f012e377ebc15095fe57942cff0
parentfe963a861851fb5b1463f8d4ab20a1b6138d3efd
[AArch64][GlobalISel] Add support for some across-vector NEON intrinsics

Support uaddv, saddv, umaxv, smaxv, uminv, sminv, fmaxv, fminv,
fmaxnmv, fminnmv intrinsics in GlobalISel.

GlobalISelEmitter couldn't import SelectionDAG patterns containing nodes
with 8-bit result type, since they had untyped values. Therefore,
register type for FPR8 is set to i8 to eliminate untyped nodes in these
patterns.

Differential Revision: https://reviews.llvm.org/D146531
llvm/lib/Target/AArch64/AArch64InstrGISel.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
llvm/test/CodeGen/AArch64/aarch64-addv.ll
llvm/test/CodeGen/AArch64/arm64-fminv.ll
llvm/test/CodeGen/AArch64/arm64-neon-across.ll
llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll