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author	Jonas Paulsson <paulsson@linux.vnet.ibm.com>
	Thu, 1 Dec 2022 18:29:24 +0000 (13:29 -0500)
committer	Jonas Paulsson <paulsson@linux.vnet.ibm.com>
	Thu, 1 Dec 2022 18:29:24 +0000 (13:29 -0500)
commit	8ef4632681227661ca3c4b608298da99f8552597
tree	fec34c2313313c7681520512237f7b47518b69c3	tree \| snapshot
parent	6d12599fd4134c1da63198c74a25490d28c733f6	commit \| diff

Revert "[CodeGen] Add new pass for late cleanup of redundant definitions."

Temporarily revert and fix buildbot failure.

This reverts commit 6d12599fd4134c1da63198c74a25490d28c733f6.

93 files changed:

llvm/include/llvm/CodeGen/CodeGenPassBuilder.h		diff \| blob \| history
llvm/include/llvm/CodeGen/MachinePassRegistry.def		diff \| blob \| history
llvm/include/llvm/CodeGen/Passes.h		diff \| blob \| history
llvm/include/llvm/InitializePasses.h		diff \| blob \| history
llvm/lib/CodeGen/CMakeLists.txt		diff \| blob \| history
llvm/lib/CodeGen/CodeGen.cpp		diff \| blob \| history
llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp	[deleted file]	blob \| history
llvm/lib/CodeGen/TargetPassConfig.cpp		diff \| blob \| history
llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp		diff \| blob \| history
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp		diff \| blob \| history
llvm/test/CodeGen/AArch64/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll		diff \| blob \| history
llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/cc-update.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/exec-mask-opt-cannot-create-empty-or-backward-segment.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/flat-scratch.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/multilevel-break.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-unify-exit-multiple-unreachables.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/si-unify-exit-return-unreachable.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll		diff \| blob \| history
llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/arm-shrink-wrapping.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/fpclamptosat.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/jump-table-islands.ll		diff \| blob \| history
llvm/test/CodeGen/ARM/reg_sequence.ll		diff \| blob \| history
llvm/test/CodeGen/BPF/objdump_cond_op_2.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll		diff \| blob \| history
llvm/test/CodeGen/Mips/llvm-ir/shl.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/cgp-select.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/fast-isel-branch.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll		diff \| blob \| history
llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/O3-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/branch-relaxation.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/rint-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/round-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir		diff \| blob \| history
llvm/test/CodeGen/RISCV/stack-realignment.ll		diff \| blob \| history
llvm/test/CodeGen/SystemZ/frame-28.mir	[deleted file]	blob \| history
llvm/test/CodeGen/Thumb/frame-access.ll		diff \| blob \| history
llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/2008-04-09-BranchFolding.ll		diff \| blob \| history
llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll		diff \| blob \| history
llvm/test/CodeGen/X86/AMX/amx-across-func.ll		diff \| blob \| history
llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fast-isel-stackcheck.ll		diff \| blob \| history
llvm/test/CodeGen/X86/fshl.ll		diff \| blob \| history
llvm/test/CodeGen/X86/masked_load.ll		diff \| blob \| history
llvm/test/CodeGen/X86/oddshuffles.ll		diff \| blob \| history
llvm/test/CodeGen/X86/opt-pipeline.ll		diff \| blob \| history
llvm/test/CodeGen/X86/sdiv_fix_sat.ll		diff \| blob \| history
llvm/test/CodeGen/X86/shift-i128.ll		diff \| blob \| history
llvm/test/CodeGen/X86/ushl_sat_vec.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_extract.ll		diff \| blob \| history
llvm/test/CodeGen/X86/vec_shift5.ll		diff \| blob \| history
llvm/test/CodeGen/XCore/scavenging.ll		diff \| blob \| history

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