riscv: errata: fix T-Head dcache.cva encoding
authorIcenowy Zheng <uwu@icenowy.me>
Tue, 12 Sep 2023 07:24:10 +0000 (15:24 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Tue, 12 Sep 2023 20:58:40 +0000 (13:58 -0700)
commit8eb8fe67e2c84324398f5983c41b4f831d0705b3
tree027912ac97c061c901aa317e68dbb27123eae477
parent1bfb2b618d52e59a4ef1896b46c4698ad2be66b7
riscv: errata: fix T-Head dcache.cva encoding

The dcache.cva encoding shown in the comments are wrong, it's for
dcache.cval1 (which is restricted to L1) instead.

Fix this in the comment and in the hardcoded instruction.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
Tested-by: Drew Fustini <dfustini@baylibre.com>
Link: https://lore.kernel.org/r/20230912072410.2481-1-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/errata_list.h