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(parent: 30b9e7e) | patch
lib: sbi_hart: clear mip csr during hart init
authorMayuresh Chitale <mchitale@ventanamicro.com>
Sat, 25 Mar 2023 16:50:47 +0000 (22:20 +0530)
committerAnup Patel <anup@brainfault.org>
Thu, 6 Apr 2023 13:22:03 +0000 (18:52 +0530)
commit8e90259da8b4b5bc6c934506cc4302578d44dbc2
tree6a38a05e971bf6d0ffcce5da92a83b738f258a6ftree | snapshot
parent30b9e7ee14498e5db805f471dbb23ea67c7a3b32commit | diff
lib: sbi_hart: clear mip csr during hart init

If mip.SEIP bit is not cleared then on HiFive Unmatched board it causes
spurious external interrupts. This breaks the boot up of HiFive Unmatched
board. Hence it is required to bring the mip CSR to a known state during
hart init and avoid spurious interrupts.

Fixes: d9e7368 ("firmware: Not to clear all the MIP")
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
firmware/fw_base.S diff | blob | history
lib/sbi/sbi_hart.c diff | blob | history
Domain: System / Kernel;