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(parent: 78e6818) | patch
[RISCV] Use LBU for extloadi8.
authorCraig Topper <craig.topper@sifive.com>
Wed, 22 Mar 2023 01:52:05 +0000 (18:52 -0700)
committerCraig Topper <craig.topper@sifive.com>
Wed, 22 Mar 2023 01:52:05 +0000 (18:52 -0700)
commit8e43c22d303835bf90a64f6732df4dfc028ac688
treed05327726a26f53667e920622487818f34512793tree | snapshot
parent78e6818049c77c90225847758ac2a317230c0197commit | diff
[RISCV] Use LBU for extloadi8.

The Zcb extension has c.lbu, but not c.lb. This patch makes us
prefer LBU over LB if we have a choice which will enable more
compression opportunities.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146270
19 files changed:
llvm/lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
llvm/test/CodeGen/RISCV/atomic-rmw.ll diff | blob | history
llvm/test/CodeGen/RISCV/atomic-signext.ll diff | blob | history
llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll diff | blob | history
llvm/test/CodeGen/RISCV/forced-atomics.ll diff | blob | history
llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll diff | blob | history
llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll diff | blob | history
llvm/test/CodeGen/RISCV/mem.ll diff | blob | history
llvm/test/CodeGen/RISCV/mem64.ll diff | blob | history
llvm/test/CodeGen/RISCV/memcpy-inline.ll diff | blob | history
llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll diff | blob | history
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll diff | blob | history
llvm/test/CodeGen/RISCV/unaligned-load-store.ll diff | blob | history
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll diff | blob | history
Domain: System / Toolchain;