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(parent: 0213541) | patch
drm/amd/display: Fix DCFCLK and SOCCLK not set
authorIlya Bakoulin <Ilya.Bakoulin@amd.com>
Thu, 28 Mar 2019 18:43:29 +0000 (14:43 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 22 Jun 2019 14:34:09 +0000 (09:34 -0500)
commit8e27a2d4cd76095c80dbbf63548175659d4b9d76
treed7ef5c0d536ba6ed87877d95775da7cdda2147ddtree | snapshot
parent0213541d4b6b241a83611dd8324af024f87b5368commit | diff
drm/amd/display: Fix DCFCLK and SOCCLK not set

[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.

[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c diff | blob | history
Domain: System / Kernel;