[Pipeliner] Fix check for order dependences when finalizing instructions
authorKrzysztof Parzyszek <kparzysz@codeaurora.org>
Mon, 26 Mar 2018 16:05:55 +0000 (16:05 +0000)
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>
Mon, 26 Mar 2018 16:05:55 +0000 (16:05 +0000)
commit8e1363df4e351c306b33f5e8896494a84b72d722
tree274e35e51cbecc10a1fe17617de7f71a95006195
parent3a0a15afe7289730238c9ea311b2823900311a3c
[Pipeliner] Fix check for order dependences when finalizing instructions

The code in orderDepdences that looks at the order dependences between
instructions was processing all the successor and predecessor order
dependences. However, we really only want to check for an order dependence
for instructions scheduled in the same cycle.

Also, fixed how the pipeliner handles output dependences. An output
dependence is also a potential loop carried dependence. The pipeliner
didn't handle this case properly so an invalid schedule could be created
that allowed an output dependence to be scheduled in the next iteration
at the same cycle.

Patch by Brendon Cahoon.

llvm-svn: 328516
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/test/CodeGen/Hexagon/swp-order-deps7.ll [new file with mode: 0644]