intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.
authorEric Anholt <eric@anholt.net>
Wed, 4 Nov 2009 01:18:36 +0000 (17:18 -0800)
committerEric Anholt <eric@anholt.net>
Fri, 6 Nov 2009 19:37:31 +0000 (11:37 -0800)
commit8e0f40d28777f1ae599a95312788fe29a0515a0d
tree4d606e40469a51808ed9541c8a67327c7341855b
parentcaf3038123d6d29afd7d1f0cd6db98a2282c3ca1
intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.

This should do all the things that MI_FLUSH did, but it can be pipelined
so that further rendering isn't blocked on the flush completion unless
necessary.
src/mesa/drivers/dri/i915/i830_vtbl.c
src/mesa/drivers/dri/i915/i915_vtbl.c
src/mesa/drivers/dri/i965/brw_draw.c
src/mesa/drivers/dri/i965/brw_vtbl.c
src/mesa/drivers/dri/intel/intel_batchbuffer.c
src/mesa/drivers/dri/intel/intel_batchbuffer.h
src/mesa/drivers/dri/intel/intel_context.h