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(parent: 48d1b36) | patch
intel_l3_parity: slice support
authorBen Widawsky <benjamin.widawsky@intel.com>
Sun, 8 Sep 2013 03:10:27 +0000 (20:10 -0700)
committerBen Widawsky <benjamin.widawsky@intel.com>
Fri, 20 Sep 2013 16:42:07 +0000 (09:42 -0700)
commit8ddcfd6882a9afd17daf5399f78f74bfc6ef3d7a
treea659f6337a531eda9b81d72a0f94e5c3a9f2dfbetree | snapshot
parent48d1b362c52803f490080be0ee26b43ae5f7dc27commit | diff
intel_l3_parity: slice support

Haswell GT3 adds a new slice which is kept distinct from the old
register interface. Plumb it into the code, though it's only 1 slice
still.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
tools/intel_l3_parity.c diff | blob | history
Domain: SCM / Uncategorized;