drm/amd/display: Fix concurrent dynamic encoder assignment.
authorJimmy Kizito <Jimmy.Kizito@amd.com>
Fri, 1 Oct 2021 14:36:19 +0000 (22:36 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Oct 2021 19:50:24 +0000 (15:50 -0400)
commit8da5cbafb2ea1c33964ed6e5c79e9f2ebe001b57
tree50eb0a799014f712c23d4621970ba6718d648854
parent1445d967fb915156aed0e79ca80c239cb2d414ce
drm/amd/display: Fix concurrent dynamic encoder assignment.

[Why]
Trying to enable multiple displays simultaneously exposed shortcomings
with the algorithm for dynamic link encoder assignment.

The main problems were:
- Assuming stream order remained constant across states would
sometimes lead to invalid DIG encoder assignment.
- Incorrect logic for deciding whether or not a DIG could support a
stream would also sometimes lead to invalid DIG encoder assignment.
- Changes in encoder assignment were wholesale while updating of the
pipe backend is incremental. This would lead to the hardware state
not matching the software state even with valid encoder assignments.

[How]

The following changes fix the identified problems.
- Use stream pointer rather than stream index to track streams across
states.
- Fix DIG compatibility check by examining the link signal type
rather than the stream signal type.
- Modify assignment algorithm to make incremental updates so software
and hardware states remain coherent.

Additionally:
- Add assertions and an encoder assignment validation
function link_enc_cfg_validate() to detect potential problems with
encoder assignment closer to their root cause.
- Reduce the frequency with which the assignment algorithm is
executed. It should not be necessary for fast state validation.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link.c