projects / platform / kernel / linux-rpi.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 651a146) | patch
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits
authorTom St Denis <tom.stdenis@amd.com>
Thu, 11 Jun 2020 11:54:13 +0000 (07:54 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:19 +0000 (01:59 -0400)
commit8d7fb7a10a825bd2e2c0fde7979cd8774c332bea
tree18230fd18156acb229eee5b2efe95b5633b83163tree | snapshot
parent651a146526a04993c5bebf0e19cd9256f5e6511dcommit | diff
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits

Even though they are technically MMIO registers I put the bits with the sqind block
for organizational purposes.

Requested for UMR debugging.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h diff | blob | history
Domain: System / Kernel;