net: stmmac: fix enabling socfpga's ptp_ref_clock
authorJulien Beraud <julien.beraud@orolia.com>
Wed, 15 Apr 2020 12:24:31 +0000 (14:24 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 10 May 2020 08:31:26 +0000 (10:31 +0200)
commit8d5a1ddaa9bbe1e18d1445240765b2a612df1b04
tree520dc6ae081c96d4517569aac20e7f32fc911a6d
parentd3539ea43a37b6dce6c59c6157966a5a6f5df483
net: stmmac: fix enabling socfpga's ptp_ref_clock

[ Upstream commit 15ce30609d1e88d42fb1cd948f453e6d5f188249 ]

There are 2 registers to write to enable a ptp ref clock coming from the
fpga.
One that enables the usage of the clock from the fpga for emac0 and emac1
as a ptp ref clock, and the other to allow signals from the fpga to reach
emac0 and emac1.
Currently, if the dwmac-socfpga has phymode set to PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII, or PHY_INTERFACE_MODE_SGMII, both registers will
be written and the ptp ref clock will be set as coming from the fpga.
Separate the 2 register writes to only enable signals from the fpga to
reach emac0 or emac1 when ptp ref clock is not coming from the fpga.

Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c