ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses
authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>
Tue, 1 Aug 2017 09:58:47 +0000 (12:58 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 30 Aug 2017 08:21:46 +0000 (10:21 +0200)
commit8d362cb3bfbbaea8f3ea44d785408c719b5f6cef
treea426cec54f631c64cc05c69599383d581135c388
parent6cba07468521d4ffbebd59363a7d0bc5962b1002
ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses

commit 7d79cee2c6540ea64dd917a14e2fd63d4ac3d3c0 upstream.

It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1
which hold MSB bits of the physical address correspondingly of region start
and end otherwise SLC region operation is executed in unpredictable manner

Without this patch, SLC flushes on HSDK (IOC disabled) were taking
seconds.

Reported-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: PAR40 regs only written if PAE40 exist]
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arc/include/asm/cache.h
arch/arc/mm/cache.c