[DAGCombiner] narrow truncated binops
authorSanjay Patel <spatel@rotateright.com>
Thu, 29 Nov 2018 20:58:26 +0000 (20:58 +0000)
committerSanjay Patel <spatel@rotateright.com>
Thu, 29 Nov 2018 20:58:26 +0000 (20:58 +0000)
commit8d271442514409323d899908553c290d1c3faba4
tree4b191ffa0a28fbffae7c844f02d5844dfb80f700
parentc1410635bfa8979862606056b5fc1eb5db4840e5
[DAGCombiner] narrow truncated binops

The motivating case for this is shown in:
https://bugs.llvm.org/show_bug.cgi?id=32023
and the corresponding rot16.ll regression tests.

Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc
sequences that don't get folded in IR.

As the TODO comments suggest, there will be regressions if we extend this (for x86,
we mostly seem to be missing LEA opportunities, but there are likely vector folds
missing too). I think those should be considered existing bugs because this is the
same transform that we do as an IR canonicalization in instcombine. We just need
more tests to make those visible independent of this patch.

Differential Revision: https://reviews.llvm.org/D54640

llvm-svn: 347917
23 files changed:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
llvm/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
llvm/test/CodeGen/X86/add-sub-nsw-nuw.ll
llvm/test/CodeGen/X86/bool-math.ll
llvm/test/CodeGen/X86/clear-lowbits.ll
llvm/test/CodeGen/X86/cmov.ll
llvm/test/CodeGen/X86/extract-bits.ll
llvm/test/CodeGen/X86/extract-lowbits.ll
llvm/test/CodeGen/X86/fshl.ll
llvm/test/CodeGen/X86/fshr.ll
llvm/test/CodeGen/X86/funnel-shift-rot.ll
llvm/test/CodeGen/X86/funnel-shift.ll
llvm/test/CodeGen/X86/pr32284.ll
llvm/test/CodeGen/X86/pr37879.ll
llvm/test/CodeGen/X86/rot16.ll
llvm/test/CodeGen/X86/rotate.ll
llvm/test/CodeGen/X86/rotate4.ll
llvm/test/CodeGen/X86/schedule-x86-64-shld.ll
llvm/test/CodeGen/X86/scheduler-backtracking.ll
llvm/test/CodeGen/X86/test-shrink.ll
llvm/test/CodeGen/X86/xchg-nofold.ll