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(parent: a6f5360) | patch
net/mlx5: Expose shared buffer registers bits and structs
authorMaher Sanalla <msanalla@nvidia.com>
Mon, 28 Nov 2022 16:00:17 +0000 (18:00 +0200)
committerSaeed Mahameed <saeedm@nvidia.com>
Wed, 11 Jan 2023 05:24:39 +0000 (21:24 -0800)
commit8d231dbc3b10155727bcfa9e543d397ad357f14f
treed5ce74c6795a57eab9510deb6cdd68f0e66c2bc1tree | snapshot
parenta6f536063b69102adf3588fbc0bb4f08d6c8cb82commit | diff
net/mlx5: Expose shared buffer registers bits and structs

Add the shared receive buffer management and configuration registers:
1. SBPR - Shared Buffer Pools Register
2. SBCM - Shared Buffer Class Management Register

Signed-off-by: Maher Sanalla <msanalla@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
include/linux/mlx5/driver.h diff | blob | history
include/linux/mlx5/mlx5_ifc.h diff | blob | history
Domain: System / Kernel;