ARM: perf: Set ARMv7 SDER SUNIDEN bit
authorMartin Fuzzey <mfuzzey@parkeon.com>
Thu, 14 Jan 2016 04:36:26 +0000 (23:36 -0500)
committerWill Deacon <will.deacon@arm.com>
Mon, 25 Jan 2016 18:37:44 +0000 (18:37 +0000)
commit8d1a0ae724ad74ef7946a45e3b2d3e01f39df02b
tree95c4e633c5ef8ae16bd3233ecee9f5e1e2b66623
parent92e963f50fc74041b5e9e744c330dca48e04f08d
ARM: perf: Set ARMv7 SDER SUNIDEN bit

ARMv7 counters other than the CPU cycle counter only work if the Secure
Debug Enable Register (SDER) SUNIDEN bit is set.

Since access to the SDER is only possible in secure state, it will
only be done if the device tree property "secure-reg-access" is set.

Without this:

 Performance counter stats for 'sleep 1':

          14606094 cycles                    #    0.000 GHz
                 0 instructions              #    0.00  insns per cycle

After applying:

 Performance counter stats for 'sleep 1':

           5843809 cycles
           2566484 instructions              #    0.44  insns per cycle

       1.020144000 seconds time elapsed

Some platforms (eg i.MX53) may also need additional platform specific
setup.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Pooya Keshavarzi <Pooya.Keshavarzi@de.bosch.com>
Signed-off-by: George G. Davis <george_davis@mentor.com>
[will: add warning if property is found on arm64]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Documentation/devicetree/bindings/arm/pmu.txt
arch/arm/kernel/perf_event_v7.c
drivers/perf/arm_pmu.c
include/linux/perf/arm_pmu.h