ARM: socfpga: dts: Add div-reg to the main_pll clocks
authorDinh Nguyen <dinguyen@altera.com>
Wed, 16 Apr 2014 20:05:15 +0000 (15:05 -0500)
committerDinh Nguyen <dinguyen@altera.com>
Tue, 6 May 2014 03:33:18 +0000 (22:33 -0500)
commit8cb289ed60668d3350dda5aa19b4fa1dce1c07f1
tree2c254d8089be3b05be5db6db16f07d23ab11986d
parent16fb4f8bd59e0e954991f624bcc53dad2052ef0d
ARM: socfpga: dts: Add div-reg to the main_pll clocks

The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Documentation/devicetree/bindings/clock/altr_socfpga.txt
arch/arm/boot/dts/socfpga.dtsi