Delay outgoing register assignments to last.
authorAmara Emerson <amara@apple.com>
Mon, 27 Sep 2021 06:20:46 +0000 (23:20 -0700)
committerAmara Emerson <amara@apple.com>
Mon, 4 Oct 2021 19:33:20 +0000 (12:33 -0700)
commit8bde5e58c02c14b43904e9c2e08cca1ab20fafe5
treee9d54ef7c7684e0d3a58fdea4fb37310a298ff53
parent01d696e563545d54852013416dc570b26a085fd7
Delay outgoing register assignments to last.

The delayed stack protector feature which is currently used for SDAG (and thus
allows for more commonly generating tail calls) depends on being able to extract
the tail call into a separate return block. To do this it also has to extract
the vreg->physreg copies that set up the call's arguments, since if it doesn't
then the call inst ends up using undefined physregs in it's new spliced block.

SelectionDAG implementations can do this because they delay emitting register
copies until  *after* the stack arguments are set up. GISel however just
processes and emits the arguments in IR order, so stack arguments always end up
last, and thus this breaks the code that looks for any register arg copies that
precede the call instruction.

This patch adds a thunk argument to the assignValueToReg() and custom assignment
hooks. For outgoing arguments, register assignments use this return param to
return a thunk that does the actual generating of the copies. We collect these
until all the outgoing stack assignments have been done and then execute them,
so that the copies (and perhaps some artifacts like G_SEXTs) are placed after
any stores.

Differential Revision: https://reviews.llvm.org/D110610
30 files changed:
llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
llvm/lib/Target/ARM/ARMCallLowering.cpp
llvm/lib/Target/M68k/GlSel/M68kCallLowering.cpp
llvm/lib/Target/M68k/GlSel/M68kCallLowering.h
llvm/lib/Target/Mips/MipsCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
llvm/lib/Target/X86/X86CallLowering.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-arguments.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-implicit-args.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-return-values.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sibling-call.ll
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll
llvm/test/CodeGen/Mips/GlobalISel/irtranslator/extend_args.ll
llvm/test/CodeGen/Mips/GlobalISel/irtranslator/float_args.ll
llvm/test/CodeGen/Mips/GlobalISel/irtranslator/stack_args.ll
llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp