[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
authorBradley Smith <bradley.smith@arm.com>
Mon, 8 Feb 2021 16:52:19 +0000 (16:52 +0000)
committerBradley Smith <bradley.smith@arm.com>
Thu, 18 Feb 2021 16:55:16 +0000 (16:55 +0000)
commit8bad8a43c339729bf722d519c3a25708a54bc205
treee045c20a1b48a13e90f47cf6b043057fca9b915e
parent61d4d9a5d33505727afe52f524b90943f8caf21e
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD

Adjust generateFMAsInMachineCombiner to return false if SVE is present
in order to combine fmul+fadd into fma. Also add new pseudo instructions
so as to select the most appropriate of FMLA/FMAD depending on register
allocation.

Depends on D96599

Differential Revision: https://reviews.llvm.org/D96424
13 files changed:
llvm/include/llvm/CodeGen/SelectionDAGTargetInfo.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
llvm/test/CodeGen/AArch64/sve-fp-combine.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/sve-fp.ll