review.tizen.org Git - platform/upstream/llvm.git/commit

author	eopXD <yueh.ting.chen@gmail.com>
	Sat, 24 Sep 2022 12:52:55 +0000 (05:52 -0700)
committer	eopXD <yueh.ting.chen@gmail.com>
	Tue, 27 Sep 2022 18:08:27 +0000 (11:08 -0700)
commit	8b00b24f8505970f54eab85aad8db5845a635850
tree	0935c953ca99ea334844b43d3f0a3cab6910657f	tree \| snapshot
parent	a3e60044d75823a3cd8e35de76b7bde2599fe740	commit \| diff

[VP][RISCV] Add vp.ceil and RISC-V support

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D134586

llvm/docs/LangRef.rst		diff \| blob \| history
llvm/include/llvm/IR/Intrinsics.td		diff \| blob \| history
llvm/include/llvm/IR/VPIntrinsics.def		diff \| blob \| history
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp		diff \| blob \| history
llvm/lib/Target/RISCV/RISCVISelLowering.cpp		diff \| blob \| history
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll	[new file with mode: 0644]	blob
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll	[new file with mode: 0644]	blob
llvm/unittests/IR/VPIntrinsicTest.cpp		diff \| blob \| history

Domain: System / Toolchain;