[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 6 Apr 2018 11:00:51 +0000 (11:00 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 6 Apr 2018 11:00:51 +0000 (11:00 +0000)
commit8a83f16ccd089224e7e84c0a1524296fccf61419
treed0808a41e9a7c61b8da4daa668f95106bcd7dec8
parentda8b71f292976eb64cb5a07d0ba8b5960cc3a973
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds

As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.

I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.

As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...

Differential Revision: https://reviews.llvm.org/D44654

llvm-svn: 329388
23 files changed:
llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/test/CodeGen/X86/3dnow-schedule.ll
llvm/test/CodeGen/X86/adx-schedule.ll
llvm/test/CodeGen/X86/avx-schedule.ll
llvm/test/CodeGen/X86/avx2-schedule.ll
llvm/test/CodeGen/X86/avx512-schedule.ll
llvm/test/CodeGen/X86/avx512-shuffle-schedule.ll
llvm/test/CodeGen/X86/avx512vpopcntdq-schedule.ll
llvm/test/CodeGen/X86/bmi-schedule.ll
llvm/test/CodeGen/X86/bmi2-schedule.ll
llvm/test/CodeGen/X86/clwb-schedule.ll
llvm/test/CodeGen/X86/f16c-schedule.ll
llvm/test/CodeGen/X86/fma-schedule.ll
llvm/test/CodeGen/X86/fma4-schedule.ll
llvm/test/CodeGen/X86/mmx-schedule.ll
llvm/test/CodeGen/X86/movbe-schedule.ll
llvm/test/CodeGen/X86/schedule-x86_32.ll
llvm/test/CodeGen/X86/schedule-x86_64.ll
llvm/test/CodeGen/X86/sha-schedule.ll
llvm/test/CodeGen/X86/sse41-schedule.ll
llvm/test/CodeGen/X86/tbm-schedule.ll
llvm/test/CodeGen/X86/x87-schedule.ll
llvm/test/CodeGen/X86/xop-schedule.ll