MIPS: conglomerate of multiple MIPS bugfixes and improvements

MIPS: conglomerate of multiple MIPS bugfixes and improvements

MIPS R6 is built on top of 3.10 for real HW and this patch
combines the missed patches. It is needed to do a clean and working
MIPS R6 kernel.

Squashed patches:

MIPS: Expose missing pci_io{map,unmap} declarations
MIPS: kernel: mcount.S: Drop FRAME_POINTER codepath
MIPS: malta: Move defines of reset registers and values.
MIPS: malta: Remove software reset defines from generic header.
MIPS: Boot: Compressed: Remove -fstack-protector from CFLAGS
MIPS: GIC: Fix gic_set_affinity infinite loop
MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS
MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.
MIPS: APSP: Remove <asm/kspd.h>
Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"
MIPS: Malta: Update GCMP detection.
MIPS: Fix multiple definitions of UNCAC_BASE.
MIPS: R4k clock source initialization bug fix
MIPS: use generic-y where possible
MIPS: Kconfig: Drop obsolete NR_CPUS_DEFAULT_{1,2} options
MIPS: add <dt-bindings/> symlink
MIPS: Refactor boot and boot/compressed rules
MIPS: Refactor load/entry address calculations
MIPS: Add uImage build target
MIPS: Export copy_from_user_page() (needed by lustre)
MIPS: kdump: Skip walking indirection page for crashkernels
MIPS: kexec: Fix random crashes while loading crashkernel
MIPS: Fix SMP core calculations when using MT support.
MIPS: Fix accessing to per-cpu data when flushing the cache
MIPS: Fix VGA_MAP_MEM macro.
MIPS: 74K/1074K: Correct erratum workaround.
MIPS: cpu-features.h: s/MIPS53/MIPS64/
MIPS: Kconfig: CMP support needs to select SMP as well
MIPS: Remove bogus BUG_ON()
MIPS: Always register R4K clock when selected.
MIPS: bugfix of stack trace dump.
MIPS: Add printing of ES bit when cache error occurs.
MIPS: rearrange PTE bits into fixed positions for MIPS32 R2.
MIPS: removal of X bit in page tables for HEAP/BSS.
MIPS: Add -mfp64 support to FPU emulator.
MIPS:  -mfp64 for abi=o32 ELF binaries support.
MIPS: FPU2 IEEE754-2008 SNaN support
MIPS: Revert fixrange_init() limiting to the FIXMAP region.
MIPS: 64bit address support on MIPS64 R2
MIPS: Add proAPTIV CPU support.
MIPS: MIPS32R2 Segment/EVA support upto 3GB
MIPS: Cache flush functions are reworked.
MIPS: Fix bug in using flush_cache_vunmap
MIPS: EVA CACHEE instruction implementation in kernel
MIPS: bugfix of mips_flush_data_cache_range
MIPS: Add interAptiv CPU support.
MIPS: EVA SMP support for Malta board
MIPS: Malta new memory map support
MIPS: Malta: check memory map type - legacy or new
MIPS: bugfix of Malta PCI bridges loop.
MIPS: BEV overlay segment location and size verification.
MIPS: MIPS32 R2 SYNC optimization
MIPS: configs: Add Malta EVA defconfig
MIPS: GIC: Send IPIs using the GIC.
MIPS: Malta: Remove ttyS2 serial.
MIPS/Perf-events: Fix 74K cache map
MIPS/Perf-events: Support proAptiv/interAptiv cores
MIPS: Fix more section mismatch warnings
MIPS: EVA: Fix encoding for the UUSK AM bits on the SegCtl registers.
MIPS: Malta: Enable DEVTMPFS
MIPS: Clean up MIPS MT platform configuration options.
MIPS: Fix forgotten preempt_enable() when CPU has inclusive pcaches
MIPS: malta: Fix GIC interrupt offsets
Malta default config is generated by ARCH=mips scripts/kconfig/merge_config.sh arch/mips/config/malta_defconfig android/configs/android-base.cfg android/configs/android-recommended.cfg
Input: i8042-io - Exclude mips platforms when allocating/deallocating IO regions.
MIPS: Malta buildfix of 8042 keyboard controller
Modify Malta config with the required options for booting Android
MIPS: bugfix - missed hazard barrier in xcontext setup
MIPS: proAptiv tlb exeption handler improvement - remove an excessive EHB.
MIPS: printk more cpuinfo stuff
MIPS: sead3: Remove command line from SEAD-3 device tree file.
MIPS: Added Virtuoso basic support
MIPS: Cleanup of TMR and PERFCOUNT IRQ handling
MIPS: bugfix of "core" and "vpe_id" setup for MT ASE w/out GCMP
MIPS: bugfix of force-bev-location parsing
MIPS: bugfix of ebase WG bit mask
MIPS: bugfix of coherentio variable default setup
MIPS: Accelerate LDC1/SDC1 unaligned x4 emulation
MIPS: unaligned FPU failures fix
MIPS: asm: uaccess: fix EVA support for str*_user operation
MIPS: Exclude mips platforms when allocating/deallocating IO regions by i8042
MIPS: Malta emulation: avoid using BFC00000 for L2-SYNC only feature.
MIPS: futex: Use LLE and SCE for EVA
MIPS: Bugfix of address conversion between bus and kernel virtual address
MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration
MIPS: Malta: bugfix of CPU0 status masks setup for timer and perf interrupts
MIPS: bugfix of CP0 timer/GIC clockevent driver mix
MIPS: Malta: bugfix of GIC availability check.
MIPS: Added missed GIC registers definitions
MIPS: GIC registers can be obtained now via /sys FS
MIPS: bugfix of L2-SYNC only support for CM1 cores
MIPS: CM support cleanup
MIPS: Added GCR missed register definitions
MIPS: GCR registers can be obtained now via /sys FS
MIPS: Basic CPC support
MIPS: bugfix of instruction PREFX in FPU emulator
MIPS: bugfix of CONFIG_CPU_MIPSR2 usage
MIPS: bugfix of CONFIG_CPU_MIPS64 usage
MIPS: bugfix of local atomic ops in arch/mips/include/asm/local.h
MIPS: buildfix of local atomic operations
MIPS: QEMU generic CPU support is added
MIPS: Added P5600 CPU support
MIPS: bugfix - remove unconditional R6 on P5600
MIPS: bugfix of printing 64bit address in /proc/cpuinfo
MIPS: bugfix of branch-likely emulation in branch.c
MIPS: Malta: universal memory map initialisation
MIPS: bugfix: remove a double call of decode_configs for MIPS/IMG CPUs
MIPS: bugfix of FPU save/restore for MIPS32 context on MIPS64
MIPS: msc: Prevent out-of-bounds writes to MIPS SC ioremap'd region
MIPS: bugfix: missed cache flush of TLB refill handler
MIPS: PTE bit positions slightly changed to prepare a more simple swap/file presentation
MIPS: bugfix of PTE formats for swap and file entries
MIPS: bugfix of -mfp64 in signal/signal32 context save
MIPS: yet another bugfix of -mfp64 in signal/signal32 context restore)

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>