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[ARM] Armv8.2-A FP16 code generation (part 3/3)
authorSjoerd Meijer <sjoerd.meijer@arm.com>
Tue, 6 Feb 2018 08:43:56 +0000 (08:43 +0000)
committerSjoerd Meijer <sjoerd.meijer@arm.com>
Tue, 6 Feb 2018 08:43:56 +0000 (08:43 +0000)
commit89ea2648bbdea80193e9da5657db90d411620100
tree6ff66f2837813700d9bf84114948ae0797b486f4tree | snapshot
parent2a20299f9158fb8403b9a11a1eb8f803cb4a562acommit | diff
[ARM] Armv8.2-A FP16 code generation (part 3/3)

This adds most of the FP16 codegen support, but these areas need further work:

- FP16 literals and immediates are not properly supported yet (e.g. literal
  pool needs work),
- Instructions that are generated from intrinsics (e.g. vabs) haven't been
  added.

This will be addressed in follow-up patches.

Differential Revision: https://reviews.llvm.org/D42849

llvm-svn: 324321
llvm/lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
llvm/lib/Target/ARM/ARMISelLowering.h diff | blob | history
llvm/lib/Target/ARM/ARMInstrVFP.td diff | blob | history
llvm/test/CodeGen/ARM/fp16-instructions.ll diff | blob | history
Domain: System / Toolchain;