[Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

Summary:
This patch implements semantics for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define fixed-length (VLST) versions
of existing sizeless types (VLAT).

Implemented in this patch is the the behaviour described in section 3.7.3.2
and minimal parts of sections 3.7.3.3 and 3.7.3.4, this includes:

    * Defining VLST globals, structs, unions, and local variables
    * Implicit casting between VLAT <=> VLST.
    * Diagnosis of ill-formed conditional expressions of the form:

        C ?  E1 : E2

      where E1 is a VLAT type and E2 is a VLST, or vice-versa. This
      avoids any ambiguity about the nature of the result type (i.e is
      it sized or sizeless).
    * For vectors:
        * sizeof(VLST) == N/8
        * alignof(VLST) == 16
    * For predicates:
        * sizeof(VLST) == N/64
        * alignof(VLST) == 2

VLSTs have the same representation as VLATs in the AST but are wrapped
with a TypeAttribute. Scalable types are currently emitted in the IR for
uses such as globals and structs which don't support these types, this
is addressed in the next patch with codegen, where VLSTs are lowered to
sized arrays for globals, structs / unions and arrays.

Not implemented in this patch is the behaviour guarded by the feature
macros:

    * __ARM_FEATURE_SVE_VECTOR_OPERATORS
    * __ARM_FEATURE_SVE_PREDICATE_OPERATORS

As such, the GNU __attribute__((vector_size)) extension is not available
and operators such as binary '+' are not supported for VLSTs. Support
for this is intended to be addressed by later patches.

[1] https://developer.arm.com/documentation/100987/latest

This is patch 2/4 of a patch series.

Reviewers: sdesmalen, rsandifo-arm, efriedma, cameron.mcinally, ctetreau, rengolin, aaron.ballman

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D83551