ddr: altera: Configuring SDRAM extra cycles timing parameters
authorChin Liang See <clsee@altera.com>
Wed, 21 Sep 2016 02:25:56 +0000 (10:25 +0800)
committerMarek Vasut <marex@denx.de>
Thu, 27 Oct 2016 06:03:07 +0000 (08:03 +0200)
commit89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd
tree35830c1c2691e0a2058793a03ee78fc932d92229
parent5ac5861c4ba851b473e6a24940b412b397627d8d
ddr: altera: Configuring SDRAM extra cycles timing parameters

To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
arch/arm/mach-socfpga/include/mach/sdram.h
arch/arm/mach-socfpga/qts-filter.sh
arch/arm/mach-socfpga/wrap_sdram_config.c
drivers/ddr/altera/sdram.c