Revert "[ARM] Allow D-reg copies to use VMOVD with fpregs64"
authorDavid Green <david.green@arm.com>
Thu, 1 Jun 2023 16:49:25 +0000 (17:49 +0100)
committerDavid Green <david.green@arm.com>
Thu, 1 Jun 2023 16:49:25 +0000 (17:49 +0100)
commit8998ff53c91687b1065d095f6ac0ad7578131d73
treee2f63c76d69306056f351002ad0e9efb25ccf673
parent844e9534c6d99ddb6bada740839760fa24d17cb6
Revert "[ARM] Allow D-reg copies to use VMOVD with fpregs64"

This reverts commit 0a762ec1b09d96734a3462f8792a5574d089b24d.

Some CPUs enable fp64 by default (such as cortex-m7). When specifying a
single-precision fpu with them like -mfpu=fpv5-sp-d16, the fp64 feature will
be disabled, but fpreg64 will not. We need to disable them both correctly under
clang in order for the backend to be able to use the reliably. In the meantime
this reverts 0a762ec1b09d96734 until that issue is fixed.
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/test/CodeGen/Thumb2/aapcs.ll
llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-i64-add.ll
llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
llvm/test/CodeGen/Thumb2/mve-shuffle.ll
llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
llvm/test/CodeGen/Thumb2/mve-vdup.ll
llvm/test/CodeGen/Thumb2/mve-vmovn.ll
llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll
llvm/test/CodeGen/Thumb2/vmovdrroffset.ll